Daevin Oey · Computer Engineering
I build at the boundary where chips and code have to agree — and chase bugs down the stack until the real cause shows up.
Computer engineering student at VCU, graduating December 2026. I work on FPGAs, embedded boards, firmware, and the testbenches that prove they work. After SpaceX reached out about the Embedded Software Engineer, Data Center (Starmind) role, I built the simulations below to learn — and show — the part of the job I hadn't done yet: software that keeps GPU hardware alive when it overheats, gets hit by radiation, or drops off the bus.
Four live demos — two you drive, two you press play and listen to. Same dark instrument-panel look throughout. Each is a simulation with stated, made-up numbers, not SpaceX hardware or data.
Launch an AI-compute satellite from Starbase and fly the camera as it reaches orbit. The satellite is an NVL72-class GPU rack: watch its solar / battery / thermal budget in real time, push the compute demand until it throttles — or turn the fault policy off and overclock it into a meltdown. The 72 GPUs are driven tick-for-tick by the real recorded firmware below.
Launch the lab →A C++ BMC firmware core that keeps a GPU rack alive when hardware misbehaves — radiation bit-flips, silent data corruption, a GPU falling off the PCIe bus, coolant and power faults. Every fault is a HIL-style regression test with a pass/fail answer; one scenario runs with the policy off and fails on purpose, so you can see what the firmware buys.
Open the live demo ↗A guided audio-and-diagram tour of the firmware above: the 10 Hz BMC loop, the per-GPU state machine, how it catches radiation errors and silent corruption, how it shares the power budget, and how the tests prove it. Thirteen chapters, ending in a ten-question self-quiz. Best with sound on.
Play the walkthrough →The big-picture tour of my FPGA project: I programmed a Xilinx Artix-7 to present itself as a real PCIe device, so a computer discovers it, loads a driver, and talks to it. “I built a PCIe device on an FPGA, made it enumerate and respond correctly, and verified it with a test.” This is the hardware/software boundary I want to work on.
Play the overview →The actual code behind the overview: the full pcileech-derived Vivado project — the HDL, constraints, build scripts and docs, with my changes diffable against the retained baselines. Shown view-only and watermarked. Private — you'll need the access code I share with you.
Enter the vault →FPGAs, embedded boards, firmware and the validation that shows they work. Full résumé with experience, projects, skills and education.