Daevin Oey

Computer Engineering · Hardware / Software · Embedded & FPGA

daevin04@gmail.com oeyd@vcu.edu linkedin.com/in/daevin-oey github.com/Daevin04

Summary

I'm a computer engineering student at VCU who works where hardware meets software: FPGAs, embedded boards, and the testbenches and validation that show they work. I've emulated a PCIe network controller on an FPGA for hardware validation, verified a pipelined CPU in simulation before running it on a board, and built a physical model of solar-to-home power distribution for my Dominion Energy capstone. I'm most at home tracing a bug down through the stack until the real cause shows up.

Skills

Cloud & AI

MuJoCo, Gymnasium, NVIDIA Isaac Lab, NVIDIA L4 GPUs, AWS (AI Practitioner, Cloud Practitioner), EC2, S3

Hardware & Embedded

GPIO, Raspberry Pi, ESP32-C6, Xilinx Artix-7, PCIe 2.0/3.0, DMA, OpenOCD

HDL & Systems Prog.

Python, C/C++, SystemVerilog, VHDL, Vivado, Tcl, Bash, PyTorch

Systems & Security

Embedded debugging, low-level system analysis, Linux, PCIe systems, memory mapping, Docker

Experience & System Projects

PCIe Hardware Research · Independent, VCU — Richmond, VA2025

github.com/Daevin04/fpga-riscv-cpu

Wrote SystemVerilog gateware that turns a Xilinx Artix-7 into an emulated PCIe network controller for hardware validation.
Implemented PCIe config space and BAR registers in RTL to study how Linux drivers enumerate and handle memory-mapped I/O.
Built a synthesizable RV32I RISC-V core with modular RTL, simulation testbenches, and Vivado build scripts.

Capstone Project — Dominion Energy · VCU — Richmond, VAAug 2025 – Present

Built a physical model of solar-to-home power distribution and integrated it with a live simulation through GPIO logic that keeps the hardware in sync.

FPGA Pipelined RISC CPU · VCU — Richmond, VASep 2025 – Dec 2025

github.com/Daevin04/risc-pipeline-cpu

Verified a 5-stage pipelined 16-bit RISC processor with testbenches and waveforms, then ran it on a Nexys 4 DDR board with a 7-segment PC display and board controls.
Designed the processor in VHDL with forwarding and load-use hazard detection.

ESP32 Watch · IndependentAug 2025 – Sep 2025

github.com/Daevin04/ESP32-C6-Claude-Terminal

Built a wearable vision assistant by integrating an ESP32-C6, a Raspberry Pi 5, and a camera that sends what it sees to Claude's API.

Teaching Assistant · VCU — Richmond, VAAug 2024 – Oct 2025

Helped run circuit theory and signal processing labs: prepared materials, worked with students, and graded.

Drone Coverage RL in a Procedural City · Richmond, VA2026 – Present

Traced why domain randomization had no effect: the repo never wrote mass or inertia into the MuJoCo model.
Fixed a roll/pitch extraction bug in the cascaded PID while swapping motor-RPM actions for velocity commands.
Extended the MuJoCo-drones-gym Crazyflie sim into a procedural city, limiting the agent to what a real drone could sense: 32 distance rays and a 7×7×3 local coverage map.

AI Robotics · VCU Research — Richmond, VA2024 – 2026

Built a MuJoCo/Gymnasium environment for training SAC agents to control a 6-DOF robotic arm.
Tuned observations and staged rewards until policies converged; trained up to 3M steps on L4 GPUs on the VCU cluster.

Job-Search Automation System · Independent2026 – Present

github.com/Daevin04/job-search-automation

Built a Python system of AI agents over SQLite that finds postings, tailors resumes, fills applications and checks each confirmation email.

Education

Virginia Commonwealth University

B.S. Computer Engineering · Richmond, VA · Expected December 2026

Old Dominion University

Computer Engineering coursework (transferred to VCU) · Norfolk, VA · 2022 – 2024

Coursework

Signal ProcessingCircuit TheoryComputer Architecture Data StructuresDatabase SystemsEmbedded SystemsLinear Algebra

External Affiliations

Competitive Swimmer · 2013 – Present
Scholarship Chair, Phi Gamma Delta — Richmond, VA · Apr 2022 – Present
Langley High School Swim Team — McLean, VA · 2019 – 2022